Add to ORKGA recently proposed “soft ” eFPGA methodology was used to create small amounts of programmable logic using the ASIC flow, but it incurs significant overhead. In this paper, it is shown that architecture-specific tactical standard cells can reduce the area and delay overhead of the previous approach by 58 % and 40 % respectively. It is also shown that by imposing a structured design and layout approach, the logic capacity and quality of standard-cell-based eFPGAs can be significantly improved. Finally, it is shown that our improved ASIC flow approach can create layouts that are competitive with another approach called GILES that uses custom FPGA CAD tools and non-standard cells for tile layout purposes. 1
Field Programmable Gale Arrays (FPGA) are becoming popular as an alternative to ASIC because of thei...
The functional component for an FPGA is the logic element which enables it to adapt to various hardw...
International audienceAn Application Specific Inflexible FPGA (ASIF) [12] is an FPGA with reduced fl...
Potential cost savings that come from the ability to make post fabrication changes in System-on-Chip...
International audienceThis paper presents a layout technique for scalable embedded Field Programmabl...
The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly con...
Standard Cell ASICs are well known in the IC industry and have been successfully used over the past ...
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spen...
Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry pattern...
advance, mask set costs have become prohibitively expensive. Structured application specific integra...
With increasing effort required for custom layout in deep-submicron technologies, we consider implem...
As integrated circuits become more and more complex, the ability to make post-fabrication changes wi...
This work proposes the first fine-grained configurable cell array specifically tailored for the impl...
In the deep submicron (DSM) era, design rules have become increasingly more stringent and have favo...
Gate arrays are often presented as a convenient means for ASIC prototyping. Obviously, they can both...
Field Programmable Gale Arrays (FPGA) are becoming popular as an alternative to ASIC because of thei...
The functional component for an FPGA is the logic element which enables it to adapt to various hardw...
International audienceAn Application Specific Inflexible FPGA (ASIF) [12] is an FPGA with reduced fl...
Potential cost savings that come from the ability to make post fabrication changes in System-on-Chip...
International audienceThis paper presents a layout technique for scalable embedded Field Programmabl...
The logic scaling following Moores law has reached a level where System on Chips (SoCs) commonly con...
Standard Cell ASICs are well known in the IC industry and have been successfully used over the past ...
Creating a new FPGA is a challenging undertaking because of the significant effort that must be spen...
Implementing logic blocks in an integrated circuit in terms of repeating or regular geometry pattern...
advance, mask set costs have become prohibitively expensive. Structured application specific integra...
With increasing effort required for custom layout in deep-submicron technologies, we consider implem...
As integrated circuits become more and more complex, the ability to make post-fabrication changes wi...
This work proposes the first fine-grained configurable cell array specifically tailored for the impl...
In the deep submicron (DSM) era, design rules have become increasingly more stringent and have favo...
Gate arrays are often presented as a convenient means for ASIC prototyping. Obviously, they can both...
Field Programmable Gale Arrays (FPGA) are becoming popular as an alternative to ASIC because of thei...
The functional component for an FPGA is the logic element which enables it to adapt to various hardw...
International audienceAn Application Specific Inflexible FPGA (ASIF) [12] is an FPGA with reduced fl...